Опыт работы:
от 5 года(лет)

График работы:
Полный день

Требования:
• ph.D. Or master degree in electronics engineering, computer science, etc.
• 2. Requires 5 to 6 years of relative experience in asic full chip level and logic design implementation
• experience in one of 6 fields listed below:
- hands-on experience in logic synthesis using synopsys dc ultra
- hands on experiences on static timing analysis using synopsys primetime-si
- hands-on experience in timing closure with 65nm or below technology design
- hands-on experience in dft (design for test) using synopsys dft compiler, dftmax, tetramax atpg, or mentor graphics dft tools
- hands-on experience in gate-level simulation using cadence verilog-xl or other simulators
- hands-on experience in low-power design implementation(multi-vdd, etc)
- in-depth knowledge of memory bist algorithm
- hands-on experience in ip (arm, ddr phy, usb phy, analog cores, etc.) embedded design
- scripts writing experience in shell, perl, and tcl
• good communication skills, teamwork, and problem-solving skills
• 45nm and / or 32nm design experiences would be an added advantage
requirements • understanding about physical design flow of latest technology
• experience the timing closure engineering using synopsys or magma or cadence p&r tool during 2~3 years

Должностные обязанности:
Job summary full chip-level logic design implementation
respondsibility
/ duty 1. Full chip level logic design implementation with or without co-worker depends on design complexity
2. Works on given tasks such as scan insertion, sta, timing violation fix, etc.
3. Customer satisfaction
4. Submits weekly report to his/her supervisor
department asic design team, back-end(full chip implementation) part
job summary full chip physical implementation (p&r and timing closure) for asic project